Various arrangements are known in the art for generating error correcting check bytes and their corresponding error syndromes during a read back process. ECC check bytes of error correcting systems generally represent the parity condition of a number of predetermined bit positions in the data block that is being checked. On the read back process, the data is processed in a manner which results in a corresponding number of "syndrome bytes" being generated.
The check bytes generated during the write process are compared with the check bytes generated during the read process and the results are the syndrome bytes. The syndrome bytes will be all zeros if no error has occurred in the data block and the ECC check bytes on read back. If an error has occurred, one or more of the syndrome bytes will not be all zeros, and the resulting pattern of ones and zeros indicate the type of error that has occurred and its location.
The present system is based on the concept suggested by Hamming where parity is taken over preselected bit positions on the block of data according to some systematic approach such that when the parity bits are assembled, they represent unique groups of ones and zeros for the data which has been checked. When the data and the check bytes are again read, these ECC check bytes are, in effect, exclusively OR'd with the newly generated ECC check bytes which should result in an all zeros pattern since the parity bits cancel out each other.
In many applications, such as the recording of large blocks of data of a disk file, it is necessary to store with this data error correcting check bits so that on transferring the stored data from the file back to the system, any errors that might have occurred either in the recording or the read back process can be checked and the system notified that an error has occurred or the ECC system can correct the error prior to sending it back to the host system. In such an environment, the ECC system must have the ability to operate at a relatively high rate in order not to interfere with the transfer of data between the disk file and the system. In addition, the ECC system must have the ability to append the generated ECC check bytes during the write operation to the stream of serial by bit data that is being recorded. In other words, immediately following the last byte of data to be recorded, the ECC system must supply the first check byte and the subsequent check bytes which are recorded with the data block from the host system. Similarly, on the read back process, the error syndromes which are generated to indicate whether an error has occured or not, and the type of error and its location, must be immediately available to the host system in order to prevent any erroneous data from being operated on in a subsequent operation. Further, as data transfer rates between data processing system and disk files increase to ranges of two megabytes per second, the need for a fast, efficient, simply-controlled ECC system becomes quite significant.
There is, therefore, a need for a fast, efficient, simply-controlled error correcting system which can operate at speeds comparable to machine cycle times of microprocessors and be synchronized therewith.